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GNU GENERAL PUBLIC LICENSE
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This is work in progress free software firmware for pinephone keyboard.
Enjoy!
~megi

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#!/bin/bash
set -e
rm -rf build
mkdir -p build
sdcc -mmcs51 --iram-size 256 --xram-size 2048 --code-size 0x6000 --code-loc 0x2000 --opt-code-size -I. main.c -o build/fw.ihx
makebin build/fw.ihx build/fw.bin
dd if=bootloader.bin of=build/fw.bin conv=notrunc &>/dev/null

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/**
* Pinephone Keyboard Firmware
*
* Copyright (C) 2021 Ondřej Jirman <megi@xff.cz>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __EM85F684A_H__
#define __EM85F684A_H__
__sfr __at(0x87) PCON; // Power Control
__sfr __at(0xc0) RSTSC; // Reset Source
__sfr __at(0xbf) P0_PRST; // Peripheral Reset
__sfr __at(0xee) P0_WDTKEY; // WDT Key
__sfr __at(0xef) P0_WDTCR; // WDT Control Register
__sfr __at(0x88) TCON; // Timer Control
__sfr __at(0x89) TMOD; // Timer Mode
__sfr __at(0x8a) TL0; // Timer 0 Low Byte
__sfr __at(0x8b) TL1; // Timer 1 Low Byte
__sfr __at(0x8c) TH0; // Timer 0 High Byte
__sfr __at(0x8d) TH1; // Timer 1 High Byte
__sfr __at(0x8e) CKCON0; // Clock Control 0
__sfr __at(0x8f) CKCON1; // Clock Control 1 (LOWCLK)
__sfr __at(0xa8) IE; // Interrupt Enable
__sfr __at(0xb8) IP; // Interrupt Priority
__sfr __at(0x81) SP; // Stack Pointer
__sfr __at(0x82) DPL; // Data Pointer Low
__sfr __at(0x83) DPH; // Data Pointer High
__sfr __at(0x84) DPL1; // Data Pointer Low Byte 1
__sfr __at(0x85) DPH1; // Data Pointer High Byte 1
__sfr __at(0x86) PAGESW; // Page Switch
__sfr __at(0xd0) PSW0; // Program Status Word 0
__sfr __at(0xd8) PSW1; // Program Status Word 1
__sfr __at(0xe0) ACC; // Accumulator
__sfr __at(0xf0) B; // B Register
__sfr __at(0x98) SCON; // Serial Control
__sfr __at(0x99) SBUF; // Serial Data Buffer
__sfr __at(0x80) P5; // Port 5 Data Registers
__sfr __at(0x90) P6; // Port 6 Data Registers
__sfr __at(0xa0) P7; // Port 7 Data Registers
__sfr __at(0xb0) P8; // Port 8 Data Registers
__sfr __at(0xe8) P9; // Port 9 Data Registers
__sfr __at(0xf5) P0_PHCON1; // Pull-High Control 1
__sfr __at(0xf7) P0_PHDSC1; // Port High Drive/Sink Control 1
__sfr __at(0xf9) P0_P5M0; // Port 5 Configuration Mode 0 Registers
__sfr __at(0xfa) P0_P6M0; // Port 6 Configuration Mode 0 Registers
__sfr __at(0xfb) P0_P7M0; // Port 7 Configuration Mode 0 Registers
__sfr __at(0xfc) P0_P8M0; // Port 8 Configuration Mode 0 Registers
__sfr __at(0xfd) P0_PHCON0; // Pull-High Control 0
__sfr __at(0xff) P0_PHDSC0; // Port High Drive/Sink Control 0
__sfr __at(0xf9) P1_P9M0; // Port 9 Configuration Mode 0 Registers
__sfr __at(0xfd) P1_PHCON2; // Pull-High Control 2
__sfr __at(0xff) P1_PHDSC2; // Port High Drive/Sink Control 2
__sfr __at(0xe9) P0_FLKEY; // Flash Key
__sfr __at(0xea) P0_FLCR; // Flash Control Register
__sfr __at(0xeb) P0_FPKEY; // Enhanced Protection Key
__sfr __at(0xec) P0_EPPOINTL; // Enhanced Protection Point Low Byte
__sfr __at(0xed) P0_EPPOINTH; // Enhanced Protection Point High Byte
__sfr __at(0x91) P0_ADCS; // ADCS(ADC Channel Select)
__sfr __at(0x92) P0_ADCR1; // ADC Control Register 1
__sfr __at(0x93) P0_ADCR2; // ADC Control Register 2
__sfr __at(0x94) P0_ADDH; // ADDH (Converted value AD11~AD4 of ADC)
__sfr __at(0x95) P0_ADDL; // ADDH (Converted value AD11~AD4 of ADC)
__sfr __at(0xa9) P0_TC3CR1; // TC3CR1: Timer 3 Control Register 1
__sfr __at(0xaa) P0_TC3CR2; // TC3CR1: Timer 3 Control Register 2
__sfr __at(0xab) P0_TC3DA; // Timer 3 DATA Buffer A
__sfr __at(0xac) P0_TC3DB; // Timer 3 DATA Buffer B
__sfr __at(0x9a) P0_SPIRX; // SPI Receive Data Buffer Control Register
__sfr __at(0x9b) P0_SPIBUFPTR1; // SPI Read FIFO counter(pointer) Register 1
__sfr __at(0x9c) P0_SPIBUFPTR2; // SPI Read FIFO counter(pointer) Register 2
__sfr __at(0xa1) P0_SPICON1; // SPICON1: SPI Control Register 1
__sfr __at(0xa2) P0_SPICON2; // SPICON2: SPI Control Register 2
__sfr __at(0xa3) P0_SPITDBR; // SPITDBR: SPI Transmit Data Buffer Register
__sfr __at(0xa4) P0_SPIRDBR; // SPIRDBR: SPI Receive Data Buffer Register
__sfr __at(0xa5) P0_SPISR1; // SPISR1: SPI Status Register 1
__sfr __at(0xa6) P0_SPISR2; // SPISR1: SPI Status Register 2
__sfr __at(0xa7) P0_SPITX; // SPI Transmit Data Buffer Control Register
__sfr __at(0xae) P0_ICEN; // Input-Change Enable
__sfr __at(0xaf) P0_EEXSF; // Extended External Interrupt Status Flag.
__sfr __at(0xb1) P0_EIE1; // Extended Interrupt Enable 1
__sfr __at(0xb2) P0_EIE2; // Extended Interrupt Enable 2
__sfr __at(0xb3) P0_EIE3; // Extended Interrupt Enable 3
__sfr __at(0xb5) P0_EXEN; // External Interrupt Pin Enable.
__sfr __at(0xb6) P0_EIESC1; // External Interrupt Edge Select Control 1
__sfr __at(0xb7) P0_EIESC2; // External Interrupt Edge Select Control 2
__sfr __at(0xb9) P0_EIP1; // Extended Interrupt Priority 1
__sfr __at(0xba) P0_EIP2; // Extended Interrupt Priority 2
__sfr __at(0xbb) P0_EIP3; // Extended Interrupt Priority 3
__sfr __at(0xc1) P0_I2CACR1; // I2CA Status and Control Register 1
__sfr __at(0xc2) P0_I2CACR2; // I2CA Status and Control Register 2
__sfr __at(0xc3) P0_I2CASA; // I2CA Slave Address Register
__sfr __at(0xc4) P0_I2CADB; // I2CA Data Buffer Register
__sfr __at(0xc5) P0_I2CADAL; // I2CA Device Address Register L
__sfr __at(0xc6) P0_I2CADAH; // I2CA Device Address Register H
__sfr __at(0xc7) P0_I2CASF; // I2CA status flag
__sfr __at(0xcd) P0_DEVPD1; // Peripheral power down
__sfr __at(0xce) P0_DEVPD2; // Peripheral power down
__sfr __at(0xcf) P0_DEVPD3; // Peripheral power down
__sfr __at(0xd1) P0_SMBTO1; // SMbus Time Out 1 Register
__sfr __at(0xd2) P0_SMBTR1; // SMbus Timer reload 1 Register
__sfr __at(0xd3) P0_SMBTO2; // SMbus Time Out 2 Register
__sfr __at(0xd4) P0_SMBTR2; // SMbus Timer reload 2 Register
__sfr __at(0xd5) P0_SMBTO3; // SMbus Time Out 3 Register
__sfr __at(0xd6) P0_SMBTR3; // SMbus Timer reload 3 Register
__sfr __at(0xd7) P0_I2CBINT; // I2C interrupt status and control register
__sfr __at(0xd9) P0_I2CBCR1; // I2CB status and control register 1
__sfr __at(0xda) P0_I2CBCR2; // I2CB status and control register 2
__sfr __at(0xdb) P0_I2CBSA; // I2CB Slave Address Register
__sfr __at(0xdc) P0_I2CBDB; // I2CB Data Buffer Register
__sfr __at(0xdd) P0_I2CBDAL; // I2CB Device Address Register L
__sfr __at(0xde) P0_I2CBDAH; // I2CB Device Address Register H
__sfr __at(0xdf) P0_I2CBCR3; // I2CB status and control register 3
__sfr __at(0xe1) P0_I2CBCR4; // I2CB status and control register 4
__sfr __at(0xe2) P0_I2CBAUTOCNT; // I2C SCL auto-counter
__sfr __at(0xe3) P0_I2CBSCLFIR; // I2CB SCL digital filter
__sfr __at(0xe4) P0_I2CBSDAFIR; // I2CB SDA digital filter
__sfr __at(0xe5) P0_I2CBSTASU; // I2C start/stop setup time timing register
__sfr __at(0xe6) P0_I2CBSTADH; // I2C start/stop hold time timing register
__sfr __at(0x91) P1_IRCTEST; // IRC Test Control Register
__sfr __at(0xa1) P1_STBCNT; // IRC Stable Count Register
__sfr __at(0xa2) P1_IRCCTRL; // IRC Control Register
__sfr __at(0xa3) P1_RETRIMTIME; // IRC Re-Trim Period Register
__sfr __at(0xa4) P1_IRCFCVAL; // IRC FC Value Register
__sfr __at(0xa5) P1_IRCCAVAL; // IRC CA Value Register
__sfr __at(0xa6) P1_IRCFRVAL; // IRC FR Value Register
__sfr __at(0xa7) P1_AUTOTRIMSTA; // IRC Auto-Trim Status Register
__sfr __at(0xa9) P1_MTFCCTRL; // IRC Manual-Trim FC Value Control Register
__sfr __at(0xaa) P1_MTCACTRL; // IRC Manual-Trim CA Value Control Register
__sfr __at(0xab) P1_MTFRCTRL; // IRC Manual-Trim FR Value Control Register
__sfr __at(0xac) P1_SOFCNTL; // IRC SOF Count Low Byte Register
__sfr __at(0xad) P1_SOFCNTH; // IRC SOF Count Low Byte Register
__sfr __at(0xae) P1_UDCACKCTRL; // UDC ACK Interrupt Control Register
__sfr __at(0xaf) P1_EPASCTRL; // Endpoint Access Control Register
__sfr __at(0xb1) P1_UDCCTRL; // UDCCTRL: UDC Control Register
__sfr __at(0xb2) P1_UDCSTA; // UDC Status Register
__sfr __at(0xb3) P1_UDCCFSTA; // UDC Load Configuration Status Register
__sfr __at(0xb4) P1_UDCCFDATA; // UDC Load Configuration Data Register
__sfr __at(0xb5) P1_UDCINT0EN; // UDC Interrupt0 Enable Register
__sfr __at(0xb6) P1_UDCINT1EN; // UDC Interrupt1 Enable Register
__sfr __at(0xb7) P1_UDCINT2EN; // UDC Interrupt2 Enable Register
__sfr __at(0xb9) P1_UDCINT0STA; // UDC Interrupt0 Status Register
__sfr __at(0xba) P1_UDCINT1STA; // UDC Interrupt1 Status Register
__sfr __at(0xbb) P1_UDCINT2STA; // UDC Interrupt2 Status Register
__sfr __at(0xbc) P1_UDCEPCTRL; // Device End-point Control Register
__sfr __at(0xbd) P1_UDCEPBUF0CTRL; // Device End-point Buffer0 Control Register
__sfr __at(0xbe) P1_UDCEPBUF1CTRL; // Device End-point Buffer1 Control Register
__sfr __at(0xbf) P1_UDCEP0BUFDATA; // UDC Endpoint0 Data Register
__sfr __at(0xc1) P1_UDCEP1BUFDATA; // UDC Endpoint1 Data Register
__sfr __at(0xc2) P1_UDCEP2BUFDATA; // UDC Endpoint2 Data Register
__sfr __at(0xc3) P1_UDCEP3BUFDATA; // UDC Endpoint3 Data Register
__sfr __at(0xc4) P1_UDCEP4BUFDATA; // UDC Endpoint4 Data Register
__sfr __at(0xc5) P1_UDCBUFSTA; // UDC Buffer Status Register
__sfr __at(0xc9) P1_UDCEP1DATAINCNT; // UDC Endpoint1 Data In Count Register
__sfr __at(0xca) P1_UDCEP1DATAOUTCNT; // UDC Endpoint1 Data Out Count Register
__sfr __at(0xcb) P1_UDCEP2DATAINCNT; // UDC Endpoint2 Data In Count Register
__sfr __at(0xcc) P1_UDCEP2DATAOUTCNT; // UDC Endpoint2 Data Out Count Register
__sfr __at(0xcd) P1_UDCEP3DATAINCNT; // UDC Endpoint3 Data In Count Register
__sfr __at(0xce) P1_UDCEP3DATAOUTCNT; // UDC Endpoint3 Data Out Count Register
__sfr __at(0xcf) P1_UDCEP4DATAINCNT; // UDC Endpoint4 Data In Count Register
__sfr __at(0xd1) P1_UDCEP4DATAOUTCNT; // UDC Endpoint4 Data Out Count Register
__sfr __at(0xd2) P1_UDCEP1BUFDEPTH; // UDC Endpoint1 Buffer Depth Register
__sfr __at(0xd3) P1_UDCEP2BUFDEPTH; // UDC Endpoint2 Buffer Depth Register
__sfr __at(0xd4) P1_UDCEP3BUFDEPTH; // UDC Endpoint3 Buffer Depth Register
__sfr __at(0xd5) P1_UDCEP4BUFDEPTH; // UDC Endpoint4 Buffer Depth Register
__sfr __at(0xd6) P1_PHYTEST0; // PHY Test0 Mode Register
__sfr __at(0xd7) P1_PHYTEST1; // PHY Test1 Mode Register
__sfr __at(0xd9) P1_UDCRESCTRL; // UDC Response Control Register
__sfr __at(0xda) P1_USBCTRL; // UDC ACK Interrupt Control Register
__sfr __at(0xdb) P1_SE1CTL; // SE1 Control register
__sfr __at(0xdc) P1_PWMDTR; // PWMA Control Register
__sfr __at(0xdd) P1_PWMDTCR; // Dead Time Control Register
__sfr __at(0xde) P1_TMREN; // PWM Source Clock Control Register
__sfr __at(0xdf) P1_PWMSF; // PWM Status Flag
__sfr __at(0xe1) P1_PWMACR; // PWMA Control Register
__sfr __at(0xe2) P1_PRDAL; // Low Byte of PWMA Period
__sfr __at(0xe4) P1_DTAL; // Low Byte of PWMA Duty
__sfr __at(0xe6) P1_TMRAL; // Low Byte of PWMA Timer
__sfr __at(0xe9) P1_PWMBCR; // PWMB Control Register
__sfr __at(0xea) P1_PRDBL; // Low Byte of PWMB Period
__sfr __at(0xec) P1_DTBL; // Low Byte of PWMB Timer
__sfr __at(0xee) P1_TMRBL; // Low Byte of PWMB Timer
__sfr __at(0xf1) P1_PWMCCR; // PWMC Control Register
__sfr __at(0xf2) P1_PRDCL; // Low Byte of PWMC Period
__sfr __at(0xf4) P1_DTCL; // Low Byte of PWMB Timer
__sfr __at(0xf6) P1_TMRCL; // Low Byte of PWMB Timer
__sbit __at(0xc7) SWRSF; // Software Reset Force and Flag
__sbit __at(0xc2) WTSF; // Watchdog Reset Flag.
__sbit __at(0xc0) PORSF; // Power-On Flag
__sbit __at(0x8f) TF1; // Timer 1 Overflow Flag.
__sbit __at(0x8e) TR1; // Timer 1 Run Control.
__sbit __at(0x8d) TF0; // Timer 0 Overflow Flag.
__sbit __at(0x8c) TR0; // Timer 0 Run Control.
__sbit __at(0x8b) IE1; // External Interrupt 1 Status Flag
__sbit __at(0x8a) IT1; // External Interrupt 1 Type Select
__sbit __at(0x89) IE0; // External Interrupt 0 Status Flag
__sbit __at(0x88) IT0; // External Interrupt 0 Type Select
__sbit __at(0xaf) EA; // Enable All Interrupt
__sbit __at(0xae) ICIE; // Input-Change Interrupts
__sbit __at(0xac) ES0; // Enable UART Interrupt
__sbit __at(0xab) ET1; // Enable Timer 1 Interrupt
__sbit __at(0xaa) EX1; // Enable External Interrupt 1.
__sbit __at(0xa9) ET0; // Enable Timer 0 Interrupt
__sbit __at(0xa8) EX0; // Enable External Interrupt 0
__sbit __at(0xbe) PICIE; // Input-Change Interrupt Priority Control.
__sbit __at(0xbc) PS0; // UART Interrupt Priority Control.
__sbit __at(0xbb) PT1; // Timer 1 Interrupt Priority Control.
__sbit __at(0xba) PX1; // External Interrupt 1 Priority Control.
__sbit __at(0xb9) PT0; // Timer 0 Interrupt Priority Control.
__sbit __at(0xb8) PX0; // External Interrupt 0 Priority Control
__sbit __at(0xd7) CY; // Carry Flag.
__sbit __at(0xd6) AC; // Auxiliary Carry Flag
__sbit __at(0xd5) F0; // User Flag 0.
__sbit __at(0xd2) OV; // Overflow Flag.
__sbit __at(0xd1) F1; // User Flag 1
__sbit __at(0xd0) PARITY; // Parity Flag
__sbit __at(0xd8) SHSF; // System-Hold Flag
// GPIO port data register bits
__sbit __at(0x87) P57;
__sbit __at(0x86) P56;
__sbit __at(0x85) P55;
__sbit __at(0x84) P54;
__sbit __at(0x83) P53;
__sbit __at(0x82) P52;
__sbit __at(0x81) P51;
__sbit __at(0x80) P50;
__sbit __at(0x97) P67;
__sbit __at(0x96) P66;
__sbit __at(0x95) P65;
__sbit __at(0x94) P64;
__sbit __at(0x93) P63;
__sbit __at(0x92) P62;
__sbit __at(0x91) P61;
__sbit __at(0x90) P60;
__sbit __at(0xa7) P77;
__sbit __at(0xa6) P76;
__sbit __at(0xa5) P75;
__sbit __at(0xa4) P74;
__sbit __at(0xa3) P73;
__sbit __at(0xa2) P72;
__sbit __at(0xa1) P71;
__sbit __at(0xa0) P70;
__sbit __at(0xb7) P87;
__sbit __at(0xb6) P86;
__sbit __at(0xb5) P85;
__sbit __at(0xb4) P84;
__sbit __at(0xb3) P83;
__sbit __at(0xb2) P82;
__sbit __at(0xb1) P81;
__sbit __at(0xb0) P80;
__sbit __at(0xef) P97;
__sbit __at(0xee) P96;
__sbit __at(0xed) P95;
__sbit __at(0xec) P94;
__sbit __at(0xeb) P93;
__sbit __at(0xea) P92;
__sbit __at(0xe9) P91;
__sbit __at(0xe8) P90;
#define IRQ_EINT0 0 // External Interrupt 0
#define IRQ_TIMER0 1 // Timer0 Overflow
#define IRQ_EINT1 2 // External Interrupt 1
#define IRQ_TIMER1 3 // Timer1 Overflow
#define IRQ_UART0 4 // Serial Port 0
#define IRQ_PINCHANGE 6 // PIN CHANGE Interrupt 0
#define IRQ_SYSTEMHOLD 8 // System Hold Interrupt
#define IRQ_INT2_3 10 // External Interrupt 2~3
#define IRQ_SPI 11 // SPI Interrupt
#define IRQ_ADC 13 // ADC Conversion Complete
#define IRQ_TIMER2 14 // Timer2 Overflow
#define IRQ_PWMA 15 // PWMA Interrupt
#define IRQ_USB 17 // USB Interrupt
#define IRQ_I2CA 20 // I2CA Interrupt
#define IRQ_PWMB 23 // PWMB Interrupt
#define IRQ_PWMC 24 // PWMC Interrupt
#define IRQ_I2CB 28 // I2CB Interrupt
#endif

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/**
* Pinephone Keyboard Firmware
*
* Copyright (C) 2021 Ondřej Jirman <megi@xff.cz>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <stdint.h>
#include <em85f684a.h>
#define BIT(n) (1u << (n))
// we just use this interrupt for wakeup from sleep on input change
void pinchange_interupt(void) __interrupt(IRQ_PINCHANGE)
{
// disable all input change interrupts
P0_ICEN = BIT(5);
}
#define T0_SET_TIMEOUT(n) { \
TL0 = 0x00; \
TH0 = (0x10000u - n) >> 8; \
TL0 = (0x10000u - n) & 0xff; \
}
#define delay_us(n) { \
TL0 = 0x00; \
TF0 = 0; \
TH0 = (0x10000u - 2 * n) >> 8; \
TL0 = (0x10000u - 2 * n) & 0xff; \
while (!TF0); \
}
// Keyboard has 12 columns and 6 rows directly connected to GPIOs.
//
// C1 P95
// C2 P96
// C3 P97
// C4 P50
// C5 P51
// C6 P52
// C7 P53
// C8 P54
// C9 P55
// C10 P56
// C11 P57
// C12 P80 (also USB IAP trigger when pulled low)
//
// R1 P60
// R2 P61
// R3 P62
// R4 P63
// R5 P64
// R6 P65
//
// INT P90
// SCL P92
// SDA P93
//
// We will want to keep keyboard controller asleep unless some key is
// pressed. If a key is pressed, the controller will continuously scan
// for further pressed keys. When all keys are released, the controller
// can go back to sleep.
//
// For this to work, we'll use port 6 ability to wake up the controller
// on change.
//
// During sleep:
// - all columns will be set to low state
// - all rows will have pull-up enabled
// - when user presses any key, row state will change to low and
// the controller will wake up
//
// During active state:
// - all columns will be put to hi-Z state, except for the currently
// scanned one, which will be in low state
// - state of rows will be read, and will indicate state of keys
// in the selected column (0 = pressed, 1 = not pressed)
//
// De-bouncing:
// - scanning will happen in 5ms intervals and only if the two
// consecutive scans match, will the result be considered valid
//
// Configure GPIO for keyboard key scanning
//
// Switch to idle state
//
// In this state we can use keyscan_idle_is_pressed() to detect whether
// any key is pressed, and switch to active mode via keyscan_active().
//
void keyscan_idle(void)
{
// enable output low on all columns (P9[7:5] P5[7:0] P8[0])
PAGESW = 0;
P5 = 0;
P8 &= 0xfe;
P9 &= 0x1f;
P0_P5M0 = 0x00;
P0_P8M0 &= 0xfe;
PAGESW = 1;
P1_P9M0 &= 0x1f;
// enable input change interrupt on port6 and clear the flag
P0_ICEN = BIT(5);
ICIE = 1;
}
uint8_t keyscan_idle_is_pressed(void)
{
return ~P6 & 0x3f;
}
//
// Switch to active mode.
//
// In this state, we can call keyscan_scan() to perform a scan.
//
void keyscan_active(void)
{
// put all columns to hi-Z (P9[7:5] P5[7:0] P8[0])
// disable input change interrupt
ICIE = 0;
PAGESW = 0;
P5 = 0;
P8 &= 0xfe;
P9 &= 0x1f;
P0_P5M0 = ~0x00u;
P0_P8M0 |= ~0xfeu;
PAGESW = 1;
P1_P9M0 |= ~0x1fu;
}
// XXX: we can debounce in the scan function too (3us?)
// 12 byte storage required
uint8_t keyscan_scan(uint8_t* res)
{
uint8_t pin, mask = 0, row;
// for each column:
// - output low on column
// - wait (for voltage to stabilize)
// - read rows
// - turn column back to hi-Z
PAGESW = 1;
for (pin = 5; pin <= 7; pin++) {
P1_P9M0 &= ~BIT(pin);
delay_us(10);
row = ~P6 & 0x3f;
mask |= row;
*res++ = row;
P1_P9M0 |= BIT(pin);
}
PAGESW = 0;
for (pin = 0; pin <= 7; pin++) {
P0_P5M0 &= ~BIT(pin);
delay_us(10);
row = ~P6 & 0x3f;
mask |= row;
*res++ = row;
P0_P5M0 |= BIT(pin);
}
P0_P8M0 &= ~BIT(0);
delay_us(10);
row = ~P6 & 0x3f;
mask |= row;
*res++ = row;
P0_P8M0 |= BIT(0);
return mask;
}
void ext_int_assert(void)
{
P90 = 0;
PAGESW = 1;
P1_P9M0 &= ~BIT(0);
}
void ext_int_deassert(void)
{
P90 = 0;
PAGESW = 1;
P1_P9M0 |= BIT(0);
}
#define I2C_N_REGS 16
static uint8_t i2c_transfer = 0x00;
static uint8_t i2c_addr = 0;
static uint8_t i2c_regs[I2C_N_REGS] = {0xaa, 0x55};
static uint8_t i2c_cmd[I2C_N_REGS];
static uint8_t i2c_cmd_len = 0;
static uint8_t go_boot = 0;
void i2c_b_interupt(void) __interrupt(IRQ_I2CB)
{
uint8_t saved_page = PAGESW;
uint8_t tmp;
PAGESW = 0;
// handle TX
if (P0_I2CBINT & BIT(7)) {
if (i2c_addr < 16)
P0_I2CBDB = i2c_regs[i2c_addr++];
else
P0_I2CBDB = 0xff;
P0_I2CBCR1 &= ~BIT(7); // clear data pending
P0_I2CBINT &= ~BIT(7);
}
// handle RX
if (P0_I2CBINT & BIT(6)) {
tmp = P0_I2CBDB;
if (i2c_cmd_len < 16)
i2c_cmd[i2c_cmd_len++] = tmp;
if (i2c_cmd_len) {
if (i2c_cmd[0] == 0xa0)
ext_int_assert();
else if (i2c_cmd[0] == 0xa1)
ext_int_deassert();
else if (i2c_cmd[0] == 0xa2)
go_boot = 1;
}
PAGESW = 0;
P0_I2CBCR1 &= ~BIT(7); // clear data pending
P0_I2CBINT &= ~BIT(6);
}
// handle stop condition
if (P0_I2CBINT & BIT(4)) {
i2c_addr = 0;
i2c_cmd_len = 0;
P0_I2CBINT &= ~BIT(4);
}
PAGESW = saved_page;
}
//
// Slave mode I2C for communication with the SoC
//
// - address is 0x15
// - 400kHz
// - interrupts are used to handle tx/rx/end of transaction (stop bit)
//
void i2c_slave_init(void)
{
PAGESW = 0;
// setup I2C B for slave mode
//P0_I2CBCR1 = 0x20;
//P0_I2CBCR2 = 0x07 << 1 | 0x01; // 400kHz mode, enable I2C B controller, enable
P0_I2CBCR1 = 0x00;
P0_I2CBCR2 = 0x07 << 1 | BIT(0); // 100kHz mode, enable I2C B controller, enable
// setup I2C address
P0_I2CBDAH = 0x00;
P0_I2CBDAL = 0x15;
P0_I2CBINT = BIT(5); // enable I2C B stop interrupt
P0_EIE3 |= BIT(5); // enable I2C B interrupt
}
void main(void)
{
uint8_t scan_active = 0;
PAGESW = 0;
// setup interrupts
EA = 0;
IE = 0;
P0_EIE1 = 0;
P0_EIE2 = 0;
P0_EIE3 = 0;
// set CPU clock to normal (high frequency) mode
// [7] = power down HS clock in low speed mode - 1: yes 0: no
// [2:1] = high speed clock pre-divider - 1: /4 2: /2 3: /1
// [0] = cpu clock mode 1: high speed mode 0: low speed mode
CKCON1 = (CKCON1 & ~0x87u) | 0x07; // 0x87
// set timer 1 and timer 0 clock source to sysclk/12 (2 MHz)
CKCON0 = 0x00;
// wait until high speed clock is stable
while (!(CKCON0 & BIT(1)));
// set both timers to 16-bit counter modes
TMOD = 0x11;
// timers clock is 2 MHz so we need to wait for 2000 ticks to get delay of 1ms
//T0_SET_TIMEOUT(2000);
// enable both timers
TCON = 0x50;
// setup watchdog (timer base is 8ms, prescaler sets up timeout /128 = ~1s)
P0_WDTCR = 0x87; // enable watchdog ~1s
P0_WDTKEY = 0x4e; // reset watchdog
// P0_WDTCR = 0x07; // disable watchdog ~1s
// P0_WDTKEY = 0xb1; // disable watchdog
// power down unused peripherlas
P0_DEVPD1 |= BIT(6) | BIT(5) | BIT(3) | BIT(1); // PWM A, timer 3, SPI, LVD
P0_DEVPD2 |= BIT(6) | BIT(3) | BIT(0); // PWM C, PWM B, I2C A
P0_DEVPD3 |= BIT(2) | BIT(1) | BIT(0); // PWM E, PWM D, PWM F
// keep UART, SPI, and I2C A in reset
//P0_PRST |= BIT(0) | BIT(2) | BIT(3);
// enable pullups only all port 6 pins and make those pins into input
PAGESW = 0;
P0_PHCON0 = 0x00;
P0_PHCON1 = 0xff; // port 6 pull-up enable
P0_P6M0 = 0xff; // port 6 input
PAGESW = 1;
P1_PHCON2 = 0x00;
// enable auto-tuning internal RC oscillator based on USB SOF packets
//P1_IRCCTRL &= ~BIT(1); // disable manual trim
i2c_slave_init();
// enable interrupts
EA = 1;
ext_int_deassert();
keyscan_idle();
while (1) {
if (go_boot) {
EA = 0;
__asm__("mov r6,#0x5a");
__asm__("mov r7,#0xe7");
__asm__("ljmp 0x0118");
}
if (scan_active) {
uint8_t active_rows = keyscan_scan(i2c_regs + 4);
if (!active_rows) {
scan_active = 0;
keyscan_idle();
// power down
//PCON |= BIT(1);
//__asm__("nop");
}
continue;
}
if (keyscan_idle_is_pressed()) {
scan_active = 1;
keyscan_active();
}
}
}

5
usb-flasher/build.sh Executable file
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#!/bin/bash
set -e
gcc -o kbprog-usb kbprog-usb.c

1
usb-flasher/fw.bin Symbolic link
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@ -0,0 +1 @@
../firmware/build/fw.bin

765
usb-flasher/kbprog-usb.c Normal file
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/**
* USB Programming tool for Pinephone keyboard
*
* Copyright (C) 2021 Ondřej Jirman <megi@xff.cz>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
// {{{ includes
#include <assert.h>
#include <errno.h>
#include <fcntl.h>
#include <inttypes.h>
#include <stdarg.h>
#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/stat.h>
#include <time.h>
#include <sys/ioctl.h>
#include <unistd.h>
#include <sys/types.h>
#include <dirent.h>
#include <linux/usbdevice_fs.h>
#define DEBUG 1
#if DEBUG
#define debug(args...) printf(args)
#else
#define debug(args...)
#endif
// }}}
// {{{ utils
static void syscall_error(int is_err, const char* fmt, ...)
{
va_list ap;
if (!is_err)
return;
fprintf(stderr, "ERROR: ");
va_start(ap, fmt);
vfprintf(stderr, fmt, ap);
va_end(ap);
fprintf(stderr, ": %s\n", strerror(errno));
exit(1);
}
static void error(const char* fmt, ...)
{
va_list ap;
fprintf(stderr, "ERROR: ");
va_start(ap, fmt);
vfprintf(stderr, fmt, ap);
va_end(ap);
fprintf(stderr, "\n");
exit(1);
}
bool read_file(const char* path, char* buf, size_t size)
{
int fd;
ssize_t ret;
fd = open(path, O_RDONLY);
if (fd < 0)
return false;
ret = read(fd, buf, size);
close(fd);
if (ret < 0)
return false;
if (ret < size) {
buf[ret] = 0;
return true;
} else {
buf[size - 1] = 0;
return false;
}
}
static int open_usb_dev(uint16_t vid, uint16_t pid)
{
char path[256], buf[256];
struct dirent *e;
unsigned e_vid, e_pid, bus, dev;
int fd = -1, ret;
DIR* d;
d = opendir("/sys/bus/usb/devices");
syscall_error(d == NULL, "opendir(/sys/bus/usb/devices) failed");
while (true) {
errno = 0;
e = readdir(d);
syscall_error(e == NULL && errno, "readdir(/sys/bus/usb/devices) failed");
if (!e)
break;
if (!strcmp(e->d_name, ".") || !strcmp(e->d_name, ".."))
continue;
snprintf(path, sizeof path,
"/sys/bus/usb/devices/%s/idVendor", e->d_name);
if (!read_file(path, buf, sizeof buf))
continue;
ret = sscanf(buf, "%x", &e_vid);
if (ret != 1)
error("Failed to parse %s", path);
snprintf(path, sizeof path,
"/sys/bus/usb/devices/%s/idProduct", e->d_name);
if (!read_file(path, buf, sizeof buf))
continue;
ret = sscanf(buf, "%x", &e_pid);
if (ret != 1)
error("Failed to parse %s", path);
if (e_vid == vid && e_pid == pid) {
snprintf(path, sizeof path,
"/sys/bus/usb/devices/%s/busnum", e->d_name);
if (!read_file(path, buf, sizeof buf))
error("Failed to read %s", path);
ret = sscanf(buf, "%u", &bus);
if (ret != 1)
error("Failed to parse %s", path);
snprintf(path, sizeof path,
"/sys/bus/usb/devices/%s/devnum", e->d_name);
if (!read_file(path, buf, sizeof buf))
error("Failed to read %s", path);
ret = sscanf(buf, "%u", &dev);
if (ret != 1)
error("Failed to parse %s", path);
snprintf(path, sizeof path,
"/dev/bus/usb/%03u/%03u", bus, dev);
debug("Found %04x:%04x at %s\n", e_vid, e_pid, path);
fd = open(path, O_RDWR);
syscall_error(fd < 0, "open(%s) failed", path);
break;
}
}
errno = ENOENT;
closedir(d);
return fd;
}
int bootloader_open(void)
{
int ret, fd;
bool had_switch = false;
// first check if keyboard USB device is available, if it is
// we need to first switch to bootloader mode
fd = open_usb_dev(0x04f3, 0x1812);
if (fd >= 0) {
for (unsigned i = 0; i <= 1; i++) {
struct usbdevfs_disconnect_claim dc = {
.interface = i,
};
ret = ioctl(fd, USBDEVFS_DISCONNECT_CLAIM, &dc);
syscall_error(ret < 0, "USBDEVFS_DISCONNECT_CLAIM failed");
}
/*
* Bootloader mode is enabled via HID SET_REPORT:SET_FEATURE
* control transfer on EP0.
*/
/* Enter IAP command payload */
uint8_t buf[8] = {
0xbc,
0x01,
};
struct usbdevfs_ctrltransfer ctrl = {
.bRequestType =
(0u << 7) // host->device
| (1u << 5) // class command
| (1u << 0), // to interface
.bRequest = 0x09, // HID SET_REPORT class command
.wValue = 0x03bc, // HID SET_FEATURE sub-command / 0xbc = enter IAP
.wIndex = 0,
.wLength = 8,
.timeout = 300,
.data = buf,
};
ret = ioctl(fd, USBDEVFS_CONTROL, &ctrl);
if (ret == 0)
error("Failed to switch keyboard to IAP programming mode");
had_switch = true;
close(fd);
}
// open the bootloader USB device (wait for it if we just switched to bootloader mode)
for (int i = 0;; i++) {
fd = open_usb_dev(0x04f3, 0x0905);
if (fd >= 0)
break;
if (!had_switch)
error("Bootloader USB device not found");
if (i > 16)
error("Bootloader USB device did not appear after switching keyboard to IAP mode");
usleep(250000);
}
for (unsigned i = 0; i <= 3; i++) {
struct usbdevfs_disconnect_claim dc = {
.interface = i,
};
ret = ioctl(fd, USBDEVFS_DISCONNECT_CLAIM, &dc);
syscall_error(ret < 0, "USBDEVFS_DISCONNECT_CLAIM failed");
}
return fd;
}
// Bootloader endpoints:
enum {
EP_CMD = 0x01,
EP_STATUS = 0x82,
EP_DATAOUT = 0x03,
EP_DATAIN = 0x84,
};
static int bootloader_fd = -1;
void bootloader_command(uint8_t req[8])
{
int ret;
struct usbdevfs_urb* reaped_urb;
struct usbdevfs_urb urb = {
.type = USBDEVFS_URB_TYPE_INTERRUPT,
.endpoint = EP_CMD,
.flags = USBDEVFS_URB_ZERO_PACKET,
.buffer = req,
.buffer_length = 8,
.actual_length = 8,
};
ret = ioctl(bootloader_fd, USBDEVFS_SUBMITURB, &urb);
syscall_error(ret < 0, "USBDEVFS_SUBMITURB failed");
ret = ioctl(bootloader_fd, USBDEVFS_REAPURB, &reaped_urb);
syscall_error(ret < 0, "USBDEVFS_REAPURB failed");
debug("CMD:");
for (int i = 0; i < urb.actual_length; i++)
debug(" %02hhx", req[i]);
debug("\n");
}
void bootloader_status(uint8_t res[4])
{
int ret;
struct usbdevfs_urb* reaped_urb;
struct usbdevfs_urb urb = {
.type = USBDEVFS_URB_TYPE_INTERRUPT,
.endpoint = EP_STATUS,
.flags = USBDEVFS_URB_SHORT_NOT_OK,
.buffer = res,
.buffer_length = 4,
.actual_length = 0,
};
ret = ioctl(bootloader_fd, USBDEVFS_SUBMITURB, &urb);
syscall_error(ret < 0, "USBDEVFS_SUBMITURB failed");
ret = ioctl(bootloader_fd, USBDEVFS_REAPURB, &reaped_urb);
syscall_error(ret < 0, "USBDEVFS_REAPURB failed");
debug("RES:");
for (int i = 0; i < urb.actual_length; i++)
debug(" %02hhx", res[i]);
debug("\n");
}
enum {
STATUS_READY = 1,
STATUS_BUSY = 2,
STATUS_SUCCESS = 3,
STATUS_FAIL = 4,
STATUS_ERROR = 5,
};
void bootloader_standard_status_check(void)
{
uint8_t res[4];
const char* msg = "Unknown";
bootloader_status(res);
uint16_t status = res[0] << 8 | res[1];
uint8_t err = res[2];
switch (status) {
case STATUS_BUSY:
printf("Busy\n");
break;
case STATUS_FAIL:
error("Fail status returned");
case STATUS_ERROR:
switch (err) {
case 0x1: msg = "Command is unknown"; break;
case 0x2: msg = "Command stage is error"; break;
case 0x3: msg = "Data stage is error"; break;
case 0x4: msg = "ROM address is error"; break;
case 0x5: msg = "Authority Key is incorrect"; break;
case 0x6: msg = "Write ROM is not finish"; break;
case 0x7: msg = "Write Option is not finish"; break;
case 0x8: msg = "Length is over"; break;
case 0x9: msg = "Length is less"; break;
case 0xa: msg = "CheckSum is incorrect"; break;
case 0xb: msg = "Write Flash is abnormal"; break;
case 0xc: msg = "It is over ROM area"; break;
case 0xd: msg = "ROM page is error"; break;
case 0xe: msg = "Flash Key is error"; break;
case 0xf: msg = "Option ROM address range error"; break;
}
error("Error status returned: %s", msg);
}
}
int bootloader_read_data(uint8_t res[64])
{
int ret;
struct usbdevfs_urb* reaped_urb;
struct usbdevfs_urb urb = {
.type = USBDEVFS_URB_TYPE_INTERRUPT,
.endpoint = EP_DATAIN,
.flags = USBDEVFS_URB_SHORT_NOT_OK,
.buffer = res,
.buffer_length = 64,
.actual_length = 0,
// .usercontext = (void*)(uintptr_t)0,
};
ret = ioctl(bootloader_fd, USBDEVFS_SUBMITURB, &urb);
syscall_error(ret < 0, "USBDEVFS_SUBMITURB failed");
ret = ioctl(bootloader_fd, USBDEVFS_REAPURB, &reaped_urb);
syscall_error(ret < 0, "USBDEVFS_REAPURB failed");
debug("DATA:");
for (int i = 0; i < urb.actual_length; i++)
debug(" %02hhx", res[i]);
debug("\n");
return urb.actual_length;
}
void bootloader_write_data(uint8_t res[64])
{
int ret;
struct usbdevfs_urb* reaped_urb;
struct usbdevfs_urb urb = {
.type = USBDEVFS_URB_TYPE_INTERRUPT,
.endpoint = EP_DATAOUT,
.flags = 0,
.buffer = res,
.buffer_length = 64,
.actual_length = 64,
// .usercontext = (void*)(uintptr_t)0,
};
ret = ioctl(bootloader_fd, USBDEVFS_SUBMITURB, &urb);
syscall_error(ret < 0, "USBDEVFS_SUBMITURB failed");
ret = ioctl(bootloader_fd, USBDEVFS_REAPURB, &reaped_urb);
syscall_error(ret < 0, "USBDEVFS_REAPURB failed");
debug("DATA:");
for (int i = 0; i < urb.actual_length; i++)
debug(" %02hhx", res[i]);
debug("\n");
}
#define CMD_TAG 0xc1
#define CMD_GETVERSPEC 0x40
#define CMD_GETVERFW 0x41
#define CMD_GETSTATUS 0x42
#define CMD_EXITAUTHMODE 0x43
#define CMD_GETAUTHLOCK 0x44
#define CMD_SETAUTHLOCK 0x45
#define CMD_ABORT 0x46
#define CMD_GETCHECKSUM 0x47
#define CMD_ENTRYIAP 0x20
#define CMD_FINISHEDIAP 0x21
#define CMD_CANCELIAP 0x23
#define CMD_SOFTWARERESET 0x24
#define CMD_BOOTCONDITION 0x25
#define CMD_WRITEROM 0xa0
#define CMD_WRITEROMFINISH 0xa1
#define CMD_WRITEOPTION 0xa2
#define CMD_WRITEOPTIONFINISH 0xa3
#define CMD_WRITECHECKSUM 0xa4
/*
* - called from WriteOptData in some cases (getVerSpec >= 0x170) or A chips
* - we probably don't need this?
*/
#define CMD_WRITECUSTOMINFO 0xa5 // 3:addr_l=0 4:addr_h=1 5:len_l 6:len_h 7:0xa9 8 :0x7f (sec key)
#define CMD_WRITECUSTOMINFOFINISH 0xa6 // 3:csum
#define CMD_READROM 0xe0
#define CMD_READROMFINISH 0xe1
#define CMD_READOPTION 0xe2
#define CMD_READOPTIONFINISH 0xe3
#define CMD_READDATAREQUEST 0xe4 // not implemented
#define AUTH_KEY [6] = 0xa9, [7] = 0x7f
uint16_t cmd_get_ver_spec(void)
{
bootloader_command((uint8_t[8]) { CMD_TAG, CMD_GETVERSPEC, });
uint8_t res[4];
bootloader_status(res);
return res[0] << 8 | res[1];
}
uint16_t cmd_get_ver_fw(void)
{
bootloader_command((uint8_t[8]) { CMD_TAG, CMD_GETVERFW, });
uint8_t res[4];
bootloader_status(res);
return res[0] << 8 | res[1];
}
enum {
DEV_STATUS_IDLE = 1,
DEV_STATUS_IAP,
DEV_STATUS_WR_ROM,
DEV_STATUS_WR_OPT,
DEV_STATUS_WR_CSUM,
DEV_STATUS_RD_ROM,
DEV_STATUS_RD_OPT,
};
uint8_t cmd_get_status(void)
{
bootloader_command((uint8_t[8]) { CMD_TAG, CMD_GETSTATUS, });
uint8_t res[4];
bootloader_status(res);
return res[2];
}
void cmd_exit_auth_mode(void)
{
bootloader_command((uint8_t[8]) { CMD_TAG, CMD_EXITAUTHMODE, });
bootloader_standard_status_check();
}
/* returns AUTHKEY */
uint8_t cmd_get_auth_lock(void)
{
bootloader_command((uint8_t[8]) { CMD_TAG, CMD_GETAUTHLOCK, });
uint8_t res[4];
bootloader_status(res);
return res[0] ^ 0x24;
}
/* expects AUTHKEY */
void cmd_set_auth_lock(uint8_t key)
{
bootloader_command((uint8_t[8]) { CMD_TAG, CMD_SETAUTHLOCK, key ^ 0x58, });
bootloader_standard_status_check();
}
void cmd_abort(void)
{
bootloader_command((uint8_t[8]) { CMD_TAG, CMD_ABORT, });
bootloader_standard_status_check();
}
void cmd_unlock(void)
{
cmd_set_auth_lock(cmd_get_auth_lock());
}
enum {
CHECKSUM_TYPE_BOOT = 0,
CHECKSUM_TYPE_MAIN = 1,
CHECKSUM_TYPE_ALL = 2, // may not work
};
uint16_t cmd_get_checksum(uint8_t type)
{
bootloader_command((uint8_t[8]) { CMD_TAG, CMD_GETCHECKSUM, type, });
uint8_t res[4];
bootloader_status(res);
return res[0] << 8 | res[1];
}
void cmd_entry_iap(void)
{
bootloader_command((uint8_t[8]) { CMD_TAG, CMD_ENTRYIAP, AUTH_KEY, });
bootloader_standard_status_check();
}
void cmd_finished_iap(void)
{
bootloader_command((uint8_t[8]) { CMD_TAG, CMD_FINISHEDIAP, AUTH_KEY, });
bootloader_standard_status_check();
}
void cmd_cancel_iap(void)
{
bootloader_command((uint8_t[8]) { CMD_TAG, CMD_CANCELIAP, });
bootloader_standard_status_check();
}
void cmd_software_reset(void)
{
bootloader_command((uint8_t[8]) { CMD_TAG, CMD_SOFTWARERESET, });
bootloader_standard_status_check();
}
enum {
BOOT_COND1_P80_ENTRY = 1,
BOOT_COND1_NO_APP_ENTRY = 2,
BOOT_COND1_APP_JUMP_ENTRY = 4,
};
uint8_t cmd_boot_condition(void)
{
bootloader_command((uint8_t[8]) { CMD_TAG, CMD_BOOTCONDITION, });
uint8_t res[4];
bootloader_status(res);
return res[2];
}
void cmd_read_option(uint8_t opts[128])
{
uint16_t addr = 128;
uint16_t len = 128;
bootloader_command((uint8_t[8]) { CMD_TAG, CMD_READOPTION,
addr & 0xff, addr >> 8,
len & 0xff, len >> 8, });
bootloader_standard_status_check();
bootloader_read_data(opts);
bootloader_read_data(opts + 64);
uint8_t csum = 0;
for (int i = 0; i < len; i++)
csum += opts[i];
bootloader_command((uint8_t[8]) { CMD_TAG, CMD_READOPTIONFINISH, csum, });
bootloader_standard_status_check();
}
void cmd_read_rom(uint8_t* data, uint16_t addr, uint16_t len)
{
bootloader_command((uint8_t[8]) { CMD_TAG, CMD_READROM,
addr & 0xff, addr >> 8,
len & 0xff, len >> 8, });
bootloader_standard_status_check();
for (int i = 0; i < len / 64; i++)
bootloader_read_data(data + 64 * i);
uint8_t csum = 0;
for (int i = 0; i < len; i++)
csum += data[i];
bootloader_command((uint8_t[8]) { CMD_TAG, CMD_READROMFINISH, csum, });
bootloader_standard_status_check();
}
void cmd_write_rom(uint8_t* data, uint16_t addr, uint16_t len)
{
bootloader_command((uint8_t[8]) { CMD_TAG, CMD_WRITEROM,
addr & 0xff, addr >> 8,
len & 0xff, len >> 8,
AUTH_KEY, });
bootloader_standard_status_check();
for (int i = 0; i < len / 64; i++)
bootloader_write_data(data + 64 * i);
uint8_t csum = 0;
for (int i = 0; i < len; i++)
csum += data[i];
bootloader_command((uint8_t[8]) { CMD_TAG, CMD_WRITEROMFINISH, csum, });
bootloader_standard_status_check();
}
// risky function, cmd_write_option(opts, 0x80, 128)
void cmd_write_option(uint8_t* data, uint16_t addr, uint16_t len)
{
bootloader_command((uint8_t[8]) { CMD_TAG, CMD_WRITEOPTION,
addr & 0xff, addr >> 8,
len & 0xff, len >> 8,
AUTH_KEY, });
bootloader_standard_status_check();
for (int i = 0; i < len / 64; i++)
bootloader_write_data(data + 64 * i);
uint8_t csum = 0;
for (int i = 0; i < len; i++)
csum += data[i];
bootloader_command((uint8_t[8]) { CMD_TAG, CMD_WRITEOPTIONFINISH, csum, });
bootloader_standard_status_check();
}
// writes checksum into the correct location in the option eeprom
void cmd_write_checksum(uint16_t csum)
{
uint16_t addr = 0xfc;
bootloader_command((uint8_t[8]) { CMD_TAG, CMD_WRITECHECKSUM,
addr & 0xff, addr >> 8,
csum & 0xff, csum >> 8,
AUTH_KEY, });
bootloader_standard_status_check();
}
// }}}
const char* dev_status_text(uint8_t status)
{
switch (status) {
case DEV_STATUS_IDLE: return "Idle";
case DEV_STATUS_IAP: return "IAP";
case DEV_STATUS_WR_ROM: return "Write ROM";
case DEV_STATUS_WR_OPT: return "Write Option";
case DEV_STATUS_WR_CSUM: return "Write Checksum";
case DEV_STATUS_RD_ROM: return "Read ROM";
case DEV_STATUS_RD_OPT: return "Read Option";
default: return "None";
}
}
const char* boot_cond_text(uint8_t status)
{
switch (status) {
case BOOT_COND1_P80_ENTRY: return "P80";
case BOOT_COND1_NO_APP_ENTRY: return "NO APP";
case BOOT_COND1_APP_JUMP_ENTRY: return "APP JUMP";
default: return "Unknown";
}
}
int main(int ac, char* av[])
{
bootloader_fd = bootloader_open();
cmd_abort();
printf("FW=0x%04hx BOOT=0x%04hx\n", cmd_get_ver_fw(), cmd_get_ver_spec());
uint8_t opts[128];
cmd_read_option(opts);
uint16_t icid = (opts[124] | opts[125] << 8) ^ (opts[121] | opts[122] << 8);
printf("ICID=%04hx\n", icid);
cmd_unlock();
uint8_t bootcond = cmd_boot_condition();
printf("Booted via %s\n", boot_cond_text(bootcond));
uint16_t csum_boot = cmd_get_checksum(CHECKSUM_TYPE_BOOT);
uint16_t csum_app = cmd_get_checksum(CHECKSUM_TYPE_MAIN);
printf("Checksums: boot=%04hx app=%04hx\n", csum_boot, csum_app);
/*
* Checksums: boot=d355 app=449b
*
* Option ROM from factory:
*
* CODE0 at 116: 0xff
* - 24MHz intosc mode, WDT disabled, 256kHz low freq mode
* CODE3 at 119: 0xff
* - eeprom and hw reset disabled
* - BITS(2..0) = reset button config
* - BIT(3) = eeprom enable
*
* 0: fc 39 01 7f
* 4: fe ff ff ff
*
* ...: ff ff ff ff
*
* 120: df // read by bootloader & 0x6 = 0x6: 24MHz,
* 121: 0a 4f // part of ICID (ICID is this value XORed with CSUM at 124, wtf?)
* 123: 20 // ???
* 124: 9b 44 // checksum (written by CMD_WRITECHECKSUM)
* 126: 49 // ???
* 127: aa // app OK flag (0xaa = ok)
*/
int fd;
uint8_t rom[0x8000];
memset(rom, 0xff, sizeof rom);
fd = open("fw.bin", O_RDONLY);
syscall_error(fd < 0, "open(fw.bin) failed");
ssize_t len = read(fd, rom, 0x8000);
close(fd);
if (len != 0x8000)
error("Invalid rom size, must be 32768 bytes");
cmd_entry_iap();
cmd_write_rom(rom + 0x2000, 0x2000, 0x600);
cmd_finished_iap();
cmd_read_rom(rom, 0, 0x8000);
fd = open("rom.bin", O_WRONLY | O_CREAT | O_TRUNC, 0666);
if (fd >= 0) {
write(fd, rom, 0x8000);
close(fd);
}
cmd_software_reset();
return 0;
}